The present invention relates to microelectronic packages or assemblies and methods of making such assemblies, and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of a package substrate, i.e., chip carrier and the contacts on the chip are bonded directly to contacts of the chip carrier by solder balls or other connecting elements. In turn, the chip carrier can be bonded to a circuit panel through terminals overlying the front face of the chip. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference.
Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding. Packages which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip-sized packages.”
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Packages and assemblies containing multiple chips are common for packaging chips that contain memory storage arrays, particularly for dynamic random access memory chips (DRAMs) and flash memory chips. Each package has many electrical connections for carrying signals, power and ground between terminals, i.e., external connection points of the package, and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extending in both horizontal and vertical directions relative to the surface of the chip.
The transmission of signals within packages to chips of multi-chip packages poses particular challenges, especially for signals common to two or more chips in the package such as clock signals, and address and strobe signals for memory chips. Within such multi-chip packages, the lengths of the connection paths between the terminals of the package and the chips can vary. The different path lengths can cause the signals to take longer or shorter times to travel between the terminals and each chip.
Travel time of a signal from one point to another is called “propagation delay” and is a function of the conductor length, the conductor's structure, i.e., width, and other dielectric or conductive structure in close proximity therewith.
Differences in the times at which a particular signal arrives at different locations is called “skew”. Differences in the times at which two different signals reach a particular location can also be called “skew”. The skew in the arrival times of a particular signal at two or more locations is a result of both propagation delay and the times at which the particular signal starts to travel towards the locations. Skew may or may not impact circuit performance. Skew often has little impact on performance when all signals in a synchronous group of signals are skewed together, in which case all signals needed for operation arrive together when needed. However, this is not the case when different signals of a group of synchronous signals needed for operation arrive at different times. In this case the skew impacts performance because the operation cannot be performed unless all needed signals have arrived.
FIG. 1 illustrates an example of signal skew and its potential impact on performance. FIG. 1 is a graph illustrating transitions in signals Addr0, Addr1, and Addr2 needed for operation by each of a plurality of memory chips, e.g., DRAM chips within a package or module. As depicted in FIG. 1, due to different propagation delays, the Addr signals arrive at the DRAM chips at different times. Thus, Addr0 transitions between low and high signal levels (or between high and low signal levels) before Addr1 transitions between signal levels. Likewise, Addr1 transitions between signal levels before Addr2 transitions between signal levels.
The problem with synchronous signals from the package arriving at the contacts of a chip at different times is that this limits the speed or frequency at which the chip can transmit or receive the signals. To function properly, all synchronous signals required for an operation need to have arrived before the operation can be performed. A consequence of synchronous signals arriving at different times is that the frequency used to clock the signals into the chip may have to decrease. FIG. 1 further illustrates two intervals based on different arrival times of the signals involved. The first interval is set up time 102 based on the interval between the latest arriving signal and the sampling clock transition labeled CK in FIG. 1. The second interval is hold time 104 which is based on the interval between the sampling clock transition CK and the earliest arriving signal in the next successive clock cycle of operation. The time at which the signals are latched into the chip within the package is indicated by “CK”. For best performance per a given clock frequency it is desirable to maximize both the setup time and hold time.
In light of the background described above, further improvements can be made to multi-chip packages and assemblies to address skew.